1. Field of the Invention
The present invention relates to a method to manufacture a coreless packaging substrate, particularly a method to manufacture a coreless packaging substrate that is applicable to non-through hole structures, to thereby increases density of circuit layout, and streamlines manufacture process.
2. Description of Related Art
With the development of the electronic industry, the research is gradually turning to high integration and miniaturization to meet the demands of multi-function, high speed, and high frequency for electronic products. Accordingly in semiconductor packaging, the circuit boards providing circuit connections among active and passive components are evolving from single layer boards to multi-layer boards in order to expand available areas of circuit layout on circuit boards within limited spaces by interlayer connection techniques, so as to accommodate higher wiring density for integrated circuits.
The process of common semiconductor devices proceeds first with providing chip carriers suitable to semiconductor chips, such as substrates or lead frames, then the chip carriers are forwarded to semiconductor packagers to proceed with chip-disposing, molding, and ball-mounting, etc.; finally, electronic devices having demanded functions are produced.
The semiconductor package structures known in the art are fabricated by mounting a semiconductor chip on the top of the substrate, followed by wire bonding or flip-chip packaging, and then forming solder balls on the back of the substrate to suffice electrical connections for a printed circuit board. Though high-number leads can be obtained compared with lead frames, usage on higher frequencies or operations at higher speed are restricted due to limited performance of the package structure attributed to lacks of both shorter paths of leads due to the core thickness and higher wiring density due to the land width of through holes.
In the method to manufacture packaging substrate, the whole steps of a conventional technique begins with a core substrate, which is then subjected to drilling, through hole electroplating, hole-plugging, and circuit formation to thereby accomplish an inner layer structure. A multi-layer carrier is then obtained through build-up processes. FIGS. 1A to 1E are schematic illustrations of a prior art. Referring to FIG. 1A, a core substrate 11 is prepared, which is composed of a core layer 111 having a predetermined thickness and a circuit layer 112 formed on the surface thereof. Meanwhile, a plurality of plating through holes 113 are formed in the core layer 111 to thereby electrically connect to the circuit layer 112. Subsequently, as shown in FIG. 1B, the core substrate 11 is subjected to a build-up process. First, a dielectric layer 12 is formed on the core substrate 11 with a plurality of openings 13 corresponding to the circuit layer 112. Then, as shown in FIG. 1C, a seed layer 14 is formed on the surface of the dielectric layer 12 by electroless plating or sputtering, and a patterned resistive layer 15 is formed on the seed layer 14, having a plurality of open areas 150 therein to thereby expose the parts of the seed layer 14. Subsequently as shown in FIG. 1D, a patterned circuit layer 16 and a plurality of conductive vias 13a are formed in the open areas 150 of the resistive layer 15 by electroplating through the seed layer 14, such that the patterned circuit layer 16 is electrically connected to circuit layer 112 through the conductive vias 13a; then the resistive layer 15 is removed and etching is carried out to thereby remove the seed layer 14 covered underneath the resistive layer 15, such that the first built-up structure 10a is formed. Finally, as shown in FIG. 1E, a second built-up structure 10b is formed on the surface of the first built-up structure by repeating the foregoing process, and layers are formed progressively in the same manner to obtain a multi-layer substrate 10.
However, in the process described above, a core substrate is formed by forming circuits on a core layer, followed by a build-up process on the core substrate, thereby forming a multi-layer substrate that complies with the required electrical design. As a result, the thickness of the final multi-layer substrate cannot be reduced, which is unfavorable to the developmental trend of a miniaturized semiconductor package structure. If the thickness of the core substrate is reduced to as thin as 60 μm or less, the manufacture of the multi-layer substrate will be seriously compromised, and the yield from the manufacture of substrate will decrease significantly.
In addition, there are extra steps in the manufacture of the core substrate, such as the hole-plugging and the scrubbing, which elevate the manufacture cost. More importantly, it is necessary to form a plurality of plating through holes in the core substrate; the diameter of the general through hole by drilling is approximately 100 μm or more, while the diameter of the conductive via (laser blind hole) is approximately 50 μm. In comparison, the process of plating through holes makes it more difficult to form a structure with finer circuits.
Moreover, in the process of multi-layer substrate described above, it is required to manufacture a core substrate prior to forming dielectric layers and circuit layers, which consequently complicates the process steps and increases the manufacture time, and raises the manufacture cost as well.
As a result, it is urgent for the industry to avoid the drawbacks of the previous technique, such as the increased thickness of substrate, low wiring density, low yield, complicated process steps, elevated manufacture time and cost.